Before our invention there existed in the IBM z/Architecture (and its predecessor architectures) the existence of instruction formats having storage addressing in the form of base register plus 12 bit unsigned displacement or the form of base register plus index register plus 12 bit unsigned displacement, as incorporated in IBM's z900 mainframe servers. Generally, the computer architecture of the z900 was described in the IBM z/Architecture Principles of Operation, Publication SA22-7832-00, (incorporated herein by reference), where section 5–2 to 5–7 describes the Instructions consisting, of two major parts: an op code and the designation of the operands that participate. The instruction formats of these currently available machines are described beginning at 5–3. It will be noted that the basic instruction formats described at 5–4 and 5–5 include the RXE format described in detail also in our prior U.S. Pat. No. 6,105,126, granted Aug. 15, 2000, and entitled “Address Bit Decoding for same Adder Circuitry for RXE Instruction Format with SAME XBD location as RX Format and Disjointed Extended Operation Code.”